1. Field of the Invention
The invention relates to data processing systems and more particularly to a superscaler pipelined microprocessor and a method and apparatus therein for causing multiple functions to be performed during each pipeline stage.
2. Description of the Related Art
Users of modern computers are demanding greater speed in the form of increased throughput (number of completed tasks per unit of time) and increased speed (reduced time it takes to complete a task). The Reduced Instruction Set Computer (RISC) architecture is one approach system designers have taken to achieve this. While there is no standard definition for the term Reduced Instruction Set Computer (RISC), there are some generally accepted characteristics of a RISC machine. Generally a RISC machine can issue and execute an instruction per clock cycle. In a RISC machine only a very few instructions can access memory, so most instructions use on-chip registers. So, a further RISC characteristic is the provision of a large number of registers on chip. In a RISC machine the user can specify in a single instruction two sources and a destination.
In U.S. Pat. No. 4,891,743 "Register Scorboarding on a Microprocessor chip" by David Budde, et al., granted on Jan. 2, 1990 and assigned to Intel Corporation, there is described apparatus for minimizing idle time when executing an instruction stream in a pipelined microprocessor by using a scoreboarding technique. A microinstruction is placed on a microinstruction bus and a microinstruction valid line is asserted. When a load microinstruction is decoded, a read operation is sent to a bus control logic, the destination register is marked as busy, and execution proceeds to the next current microinstruction. The marking provides an indication as to whether a current instruction can be executed without interfering with the completion of a previous instruction. The marking of registers gives rise to the term "scoreboarding". Execution of the current microinstruction proceeds provided that its source and destination registers are not marked "busy"; otherwise the microinstruction valid line is unasserted immediately after the current microinstruction appears on the microinstruction bus. The current microinstruction is thereby canceled and must be reissued. When data is returned as the result of a read operation, the destination registers are marked as " not busy".
The above-referred copending patent application Ser. No. 07/486,407 extends this prior scoreboarding technique to encompass all multiple cycle operations in addition to the load instruction. This is accomplished by providing means for driving a Scbok line to signal that a current microinstruction on a microinstruction bus is valid. Information is then driven on the machine bus during the first phase of a clock cycle. The source operands needed by the instruction are read during the second phase of the clock cycle. The resources needed by operands to execute the instruction are checked to see if they are not busy. The Scbok signal is asserted upon the condition that any one resource needed by the instruction is busy. Means are provided to cause all resources to cancel any work done with respect to executing the instruction to thereby make it appear to the rest of the system that the instruction never was issued. The instruction is then reissued during the next clock cycle.
The above-referenced copending patent applications Ser. No. 07/486,408 and Ser. No. 07/488,254 describe a random access (RAM) register file having multiple independent read ports and multiple independent write ports that provide the on-chip registers to support multiple parallel instruction execution. It also checks and maintains the registers scoreboarding logic as described in Ser. No. 07/486,407. The register file contains the macrocode and microcode visible RAM registers. The register file provides a high performance interface to these registers through a multi-ported access structure, allowing four reads and two writes on different registers to occur during the same machine cycle. This register file provides a structure allows multiple parallel accesses to operands which allows several operations to proceed in parallel.
To take full advantage, a processor should be organized so that it can execute code from an internal instruction cache while having the ability to add application specific modules to meet different user applications. It should be able to execute multiple instructions in one clock cycle even when doing loads and branchesd.
It is therefore an object of the invention to provide a microprocessor in which multiple instructions are executed in one clock cycle.